Fractional `N` synthesisers are commonly used in frequency synthesisers of the type used to generate a local oscillator signal for a receiver in order to generate an intermediate frequency signal when the local oscillator signal is mixed with an incoming signal. A conventional frequency synthesiser is shown in FIG. 1 as comprising a phase lock loop 2 including a voltage controlled oscillator 4 providing a synthesiser output frequency F.sub.0, this frequency being divided in a variable divider 6 by a factor a and the divided frequency F.sub.0 /a being compared in phase with a reference frequency F.sub.ref in a phase detector 8, the output of the phase detector being applied by a loop filter 10 to control the frequency of the voltage controlled oscillator 4. The variable divider is controlled by an M bit register 12 which receives a programming frequency word, the variable divider 6 determining the numeric value of the division ratio a. Thus it is possible by adjusting the value of the frequency word to vary the division ratio and hence alter the synthesiser output frequency F.sub.0 in order to tune a receiver to the various received channels. A problem with this type of frequency synthesiser is that the minimum "step" to which the synthesiser may be tuned is F.sub.ref since dF.sub.0 =F.sub.ref (a-(a-1))=F.sub.ref. In the context of frequency hopping techniques, the hopping rate is dictated by F.sub.ref together with the loop bandwidth. FIG. 2 shows a schematic form of the circuit of FIG. 1.
In order to increase the resolution of a frequency synthesiser so that smaller tuning steps can be accommodated, it is known to manipulate the division ratio; such a synthesiser is termed a fractional `N` synthesiser, since it resolves to fractions of an `N` bit word. Early forms of this technique are described in U.S. Pat. No. 3,555,446 and U.S. Pat. No. 3,582,810. More modern forms are described in UK-A-1447418, U.S. Pat. No. 3,976,945 and U.S. Pat. No. 3,928,813. Such forms are shown in general form in FIG. 3 where similar parts to those of FIG. 1 have the same reference numerals.
A digital accumulator 20 is supplied with an input which represents the fractional frequency instruction for the synthesiser while the divider is fed with the non-fractional part (e.g. 40 kHz multiple) of the frequency (i.e. N.times.40 kHz). The system obtains fine frequency control by changing the division ratio of the divider 6 between N and N+1 in response to the accumulator output. It can be seen that if the relative number of divide by N and divide by N+1 cycles is manipulated over a period of time any average frequency between N.times.40 kHz and (N+1).times.40 kHz can be achieved. The state of the N/N+1 control line 22 is set by the digital accumulator overflow. The rate at which the accumulator overflows is directly proportional to the ratio of the fractional component to the phase detector rate.
The manipulation of the divider radio inevitably generates phase perturbations. The nature of the phase perturbations is however predictable and turns out to be directly proportional to the residual content of the digital accumulator output. The residual phase jitter can be cancelled to a reasonable extent by converting the accumulator output to an analogue signal and applying it to a phase modulator 24. There is a limit to how accurately this cancellation can be achieved getting a cancellation of better than 1% can be troublesome and often good analogue cancellation results in the phase detector being operated significantly below its maximum potential frequency. The size of the analogue correction signal applied to the phase modulator also has to be scaled according to the division ratio (N) to maintain cancellation.
An improved version of fractional-N is disclosed in GB-A-2026268 which uses two accumulators but still requires analog correction in order to achieve good spurious performance and again getting good cancellation the analogue path results in the phase detector being operated at below its optimum frequency.
GB-A-2172759 discloses a frequency synthesiser of the fractional-N type including an interpolator which limit cycles to produce an output bit stream which is added to the LSB of the divider data word.